The present invention relates generally to a semiconductor device, and more particularly to a convex-shaped interconnection structure for semiconductor devices.
As CMOS transistor scaling proceeds into the deep sub-micron regime, the number of transistors on high performance, high density integrated circuits can increase to tens of millions of transistors. This requires a large number of high density metal interconnection layers. The electrical resistance and parasitic capacitance associated with these metal interconnection layers have become a major limiting factor to circuit speed of high performance integrated circuits. The current trend of decreasing the geometries of semiconductor devices to achieve better electrical performance has placed demands on alternative materials in formation of the metal interconnection layers.
The operational speed of a VLSI (very large scale integration) or ULSI (ultra large scale integration) circuit is determined by the delay time of the interconnection between the internal devices, global wires, and systems. The total delay time is given by the equation: ttotal=tgate+RC delay. The interconnection delay, defined as the RC delay, (where R is the interconnection resistance, and C is the interconnection capacitance) is one of the most important semiconductor performance factors. The challenge in today's sub-micron semiconductor device design is to reduce the RC delay. In addition, if there is a long distance between internal devices in a large chip operating at a high clock frequency, the LC delay (where L is the line inductance and C is the interconnection capacitance) becomes the dominant factor in the delay time. For long transmission lines in a large chip, using Cu/low k interconnection structures is a popular design choice to minimize the LC transfer loss.
Conventional semiconductor devices have mainly utilized aluminum for VLSI and ULSI device interconnection structures. However, as the semiconductor device geometries have decreased to the sub-micron level, alternatives to the aluminum interconnection structures must be explored to improve device reliability, reduce geometries, and lower fabrication costs. As an example, copper (Cu) based interconnection structures with a low permittivity (low K) dielectric layer are good alternatives to the deficiencies of aluminum interconnection structures. The major interconnection challenges are how to reduce the wiring resistance, capacitance, and number of migration failures. Cu is used in place of Aluminum (Al) because the Cu resistivity is much lower (1.67 u ohm-cm) than the Al resistivity (2.62 u ohm-cm). Also, the higher melting point of Cu (1083.4 degrees C.) versus Al (660 degrees C.) makes it more resistant to migration failures than Al. The EM (electro-migration) of Cu is approximately two orders of magnitude higher than that of Al. As an example of this effect, consider the wiring capacitances of parallel wires 800 nm and 400 nm thick as a function of wiring pitch (width of wires and spaces). The wiring capacitance increases as the wiring pitch is reduced because the capacitance increases as the wires come closer together. The wiring capacitance can be lowered without increasing the sheet resistance by changing the metal from Al to Cu and changing the thickness from 800 nm to 400 nm. This is because the resistivity of a Cu wire is lower than that of an Al wire. Thus, the use of Cu interconnection structures allows for easier high density interconnection design and reduces the number of interconnection levels. The reduction in interconnection layers increases the device reliability and lowers the fabrication costs. An additional method to reduce the interconnection capacitance of a Cu interconnection structure is to utilize low permittivity (low k) dielectric materials.
Copper interconnection structures are typically formed by a “damascene” process including “single damascene” process and “dual damascene” process. In the damascene process, trenches are created in the dielectric layers that form a wiring pattern with Cu deposited in the trenches for each metal layer, while the vias filled with Cu form the plugs between the interconnection layers. Disadvantages to the use of the Cu based interconnection structures are the adverse interaction between the silicon and copper materials. Cu can contaminate the silicon wafer. Therefore, to keep Cu from migrating into the silicon, a barrier layer is applied, and lines the trenches or vias in the silicon-based dielectric layer. A number of materials can be used for the diffusion barrier, such as titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or tantalum (Ta) alloys. Cu is then applied into the trenches or vias by a process, such as ECP (electro-copper deposition), and fills the trench and via. The excess Cu material is then removed by using a chemically active slurry in a chemical mechanical polishing (CMP) process.
The interconnection structure is susceptible to a barrier edge enhanced recess (BEER) problem. Due to the Galvanic effect by a different chemical potential between the interconnection structure and its surrounding barrier layer, the part of the interconnection structure interfacing with the barrier layer would have a higher polishing rate than the rest of the interconnection structure. This causes a recess formed at the interface of the barrier layer and the interconnection structure after the CMP process completes. Conventionally, a capping layer, such as an etch stop layer, would be formed atop the interconnection structure in order for constructing a damascene structure or multiple interconnection layers. Because of the recess, a void would be formed between the capping layer and the interface of the interconnection structure and the diffusion barrier layer. The void is a weak point to electro migration and stress migration, and therefore poses a potential reliability problem.
As such, what is needed is an improved interconnection structure that is free from voids formed at an interface location with its surrounding diffusion barrier layer.